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Introducing the ULPMark-CoreMark® Benchmark

Combining the industry-standard CoreMark performance benchmark with the ULPMark line of ultra-low-power benchmarks, EEMBC's ULPMark-CM provides a consistent way to evaluate both performance and energy tradeoffs in an MCU's design.

Ultra-low power optimization is critical in devices that require a decade of battery life, or rely on energy harvesting solutions from the environment.

About ULPMark

Ultra-Low Power (ULP) describes a major design challenge MCUs face today, where product expectations range from running 10 years on a single battery, to harvesting pico-Joules of energy from the environment, to reducing overall global energy demand.

MCU vendors deploy creative design techniques to reduce the energy demands of a device in its different operating modes, such as deep sleep, peripheral data transfer, and active computation. Developers cannot rely on a single datasheet number to explain the benefits of these techniques because applications require optimization tradeoffs between all three energy demands, and performance.

The EEMBC ULPMark benchmark quantifies these tradeoffs by constructing behavioral profiles that capture device operation better than a single synthetic number. And by providing a concise methodology, ULPMark reliably and equitably measures the multiple aspects of MCU energy efficiency.

The ULPMark Family of Benchmarks

Since its inception in 2012, EEMBC's ULPMark Working Group continues to develop new profiles for MCU power and energy analysis. There are currently three profiles: ULPMark-CoreMark which focuses on performance and energy efficiency of an active-mode benchmark, ULPMark-PeripheralProfile which analyzes the energy cost of MCU peripherals, and the original ULPMark-CoreProfile which characterizes the sleep and wakeup energy of an MCU.

ULPMark-CoreMark

Often designers must choose between energy efficiency and performance. This tradeoff isn't always clear, so ULPMark-CM enables this analysis by providing both measurements simultaneously. The ULPMark-CM score is the number of CoreMark iterations a device can execute per milli-Joule. This number, when presented with the CoreMark iterations-per-second score, illustrates how the two opposing metrics are related.

There are three components to every ULPMark-CM configuration: The ULPMark-CM energy-efficiency score, the voltage the score was collected at, and its CoreMark performance score. This triad of numbers succinctly defines an operating point on a performance-versus-energy curve. The benchmark defines three operating-point configurations that the developer must accommodate:

  1. A best-case "Performance [PERF]" configuration score,
  2. a best-case "Energy Efficiency [EE]" configuration score at the lowest voltage, and
  3. an "Energy Efficiency 3V [EE3V]" score collected at 3V in order to facilitate a baseline comparison across products at a same voltage.

Unlike the original CoreMark performance benchmark that had a single instance of the functions, inside ULPMark-CM the developer provides multiple versions of the CoreMark library, each one optimized for different hardware conditions. This is very different from CoreMark, where the firmware operated at one voltage and frequency. The new ULPMark-CM firmware also allows the developer to provide extensive hardware reconfiguration during the benchmark, without having to disconnect the device or flash new firmware between measurements.

ULPMark-CM (right) adds more configurability to the analysis of CoreMark (left). Instead of a single instance of the code at one condition, ULPMark-CM provides an API to analyze several operating points.

The host GUI supports a "Benchmark Mode", where the user measures the three operating points mentioned above and submit those scores to the EEMBC website, or in "Experiment Mode", where the user may explore any additional configurations supplied by the developer.

ULPMark-PeripheralProfile

ULPMark-PP focuses on the MCU's commonly used peripherals like pulse-width modulation (PWM), analog-to-digital conversion (ADC), the serial peripheral interface (SPI), and a real-time clock (RTC). This benchmark defines ten one-second activity slots each with variable usage of ADC, SPI, PWM, RTC, allowing the MCU and peripherals to sleep after their activities have completed. The following table gives an overview of the activity in each slot. As soon as the device finishes the peripheral operation for that slot it can enter sleep. This means faster peripherals will most likely score higher since they can remain off longer.

Peripheral Profile Slot Descriptions

SlotADCPWMSPIRTC
1
# samples: 64
Conversion rate: 1 kHz
Freq: 32,786 Hz, period: 255
Duty: 10%, fixed
# pulses: 20
Setup & Start Timer
2
# samples: 64
Conversion rate: 1 kHz
Buffered evaluation
Freq: 32,786 Hz, period: 255
Duty: 20%, increase
# pulses: 40
3
# samples: 1
Conversion rate: 1 Hz
Freq: 32,786 Hz, period: 255
Duty: 30%, fixed
# pulses: 40
4
# samples: 1
Conversion rate: 1 Hz
Freq: 32,786 Hz, period: 255
Duty: 40%, fixed
# pulses: 100
Tx 128 B
5
# samples: 1
Conversion rate: 1 Hz
Freq: 32,786 Hz, period: 255
Duty: 50%, fixed
# pulses: 100
Check last Rx
Tx 128 B
6
# samples: 1
Conversion rate: 1 Hz
Freq: 32,786 Hz, period: 255
Duty: 60%, fixed
# pulses: 100
Check last Rx
Tx 128 B
7
# samples: 1
Conversion rate: 1 Hz
Freq: 32,786 Hz, period: 255
Duty: 70%, fixed
# pulses: 100
Check last Rx
Tx 128 B
8
# samples: 1
Conversion rate: 1 Hz
Freq: 32,786 Hz, period: 255
Duty: 80%, fixed
# pulses: 100
Check last Rx
Tx 128 B
9
# samples: 1
Conversion rate: 1 Hz
Freq: 1 MHz, period: 10,000
Duty: 10%, increase
# pulses: 30
Check last Rx
Tx 128 B
10
Off
Check slots' 3-9 data
Off
Check last Rx
Stop & check
ULPMark-CoreProfile

The Core Profile focuses on the MCU’s core, specifically the energy cost in sleep, and the transition to and from active mode. This benchmark utilizes a common set of workloads that are portable across 8-, 16-, and 32-bit microcontrollers. The Core Profile runs on a one-second duty cycle combining these workloads with an extended period of inactivity to enable the use of microcontroller low-power modes. Please refer to the FAQ for more information on the active workload.

The ULPMark-CP benchmark operates in long periods of sleep, followed by a brief wakeup to perform minimal processing, mimicking a sleepy-edge node conserving energy.

ULPMark gets IoTConnected

ULPMark has been redesigned since it's first release in 2014. It now works with the EEMBC IoTConnect™ benchmark framework, the same one used by IoTMark and SecureMark, with a super-thin API that enables any MCU to execute next generation EEMBC benchmarks. The STMicroelectronics PowerShield provides the backbone of the framework's energy measurement, with sub-100nJ accuracy on your desktop for around US$100.

Working Group Status

All versions of ULPMark are available for corporate and academic licensing. As always, member companies and licensees are continually uploading new scores.

Join the working group to help ensure a meaningful and fair representation for your company’s products.


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