From Markus Levy

November 2014



  • EnergyMonitor and ULPBench Have Arrived
  • CoreMark Score Causes Concern
  • EEMBC Launches Cloud and Big Data Group
  • Forward Concepts Publishes AndEBench-Pro Results
  • EEMBC Presenting at Open Server Summit 2014
  • EEMBC in the News
  • On-Going Things

EnergyMonitor™ and ULPBench™ Have Arrived

EEMBC has begun shipping its EnergyMonitor.  The EnergyMonitor tool is designed to work in conjunction with EEMBC ULPBench, a method to accurately and reliably measure the energy efficiency of microcontrollers targeted at ultra-low power (ULP) applications. Cost of the EnergyMonitor is cost is $75 USD + shipping; ULPBench is included free with the purchase of the EnergyMonitor.
New features on our website include:

  • EnergyMonitor Fact Sheet
  • An example ULPBench compliant device
  • Initial test results
  • Ability for you to submit scores

CoreMark® Score Causes Concern

Recently, STMicroelectronics released its EEMBC certified score for CoreMark running on its STM32F756NGH6 (an ARM Cortex-M7 device). That score, 5.01 CoreMark/MHz, significantly leapfrogged its previous Cortex-M4 device (at 3.38 CM/MHz). When I first saw this result, my first impression was that they figured out a way to ‘beat’ CoreMark. Upon closer investigation, I noticed that all the Cortex-M7 improvements vs the Cortex-M4 are derived from the hardware. The CoreMark code used for this recent certification was exactly the same and the compiler used was not radically different. So in fact, CoreMark is doing its job perfectly, in providing a reference for measuring the relative performance of the cores.

Pin-pointing the exact reason why the M7 hardware so significantly outperformed the M4 would require profiling and runtime analysis, but at a high-level I noted that the performance increase is related to the new core having a six-stage, superscalar pipeline, as opposed to the 3-stage, single-issue pipeline on the M4. The M7 also has an L1 cache and a 64-bit AXI bus interface - although the code for the CoreMark test was located in internal flash which is located on the tightly coupled memory interface and benefitted from ST's ART "cache" rather than that of the core. So the performance enhancement is as would be expected. It is just surprising that to find this kind of performance in a low-cost, low-power microcontroller core, although the die area consumes 2-3x that of the M4.

EEMBC Launches Cloud and Big Data Group

EEMBC’s newly formed Cloud and Big-Data Server working group has a charter to build a standardized, industry-endorsed suite of performance and efficiency benchmarks that characterize SoC performance for modern cloud and big-data related workloads (scale-out computing). Initial focus is on memory caching, media streaming, and graph analytics. This working group is for data center companies, server manufacturers, and silicon providers. Contact EEMBC for more information.

Forward Concepts Publishes AndEBench-Pro™ Results

A recent newsletter from Forward Concepts has published the ‘top 10’ AndEBench-Pro performers. As analyst Will Strauss points out “What’s interesting (and perhaps unusual) is that a device might be the highest performer overall, but that might not be the case for some of its underlying components”.

EEMBC Presenting at Open Server Summit 2014

Open Server Summit 2014 focuses on combining industry standard hardware with open-source software to make servers, data centers, and networks scalable, cost effective, and capable of handling big data, cloud computing, mobile access, and mega-websites. EEMBC will present on November 11th from 3:00-4:00PM in the Scale-Out Server Track. Exhibits and Open Sessions registration is free online until November 7.

EEMBC in the News


Cloud and Big Data


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