First SuperH Processor Benchmark Now Available From EEMBC
ECL–Certified 266-MHz Simulation Scores for SH-4 Core Show Out-of-the-Box Capabilities of Processor and Compiler
EL DORADO HILLS, Calif.—October 15, 2002—The first certified benchmark scores for a processor core from SuperH, Inc. were published today by EEMBC, the Embedded Microprocessor Benchmark Consortium.
The licensable SuperH™ SH-4 CPU core is a 2-issue superscalar, 32-bit RISC core with integrated vector FPU and was tested in a 266-MHz simulation against four of EEMBC’s application-based benchmark suites using the open-source GNU gcc 3.2 Vienna 1.3 alpha compiler.
The out-of-the-box scores for the SH-4 CPU core, which were derived with no modification to the EEMBC® benchmark source code, allow designers to predict performance in automotive/industrial, consumer, networking, and office automation applications. Per-Megahertz consolidated scores in each category were .52771 Automarks, .07474 Consumermarks, .01917 Netmarks, and .67887 OAmarks.
“EEMBC benchmark scores are a significant measurement of processor performance that industry leaders have agreed upon,” said Rick Chapman, vice president of marketing and sales for SuperH, Inc. “We see publication of these SH-4 scores as validating both our belief in the EEMBC process and our confidence in the SH-4 architecture.”
The SuperH GNU compiler is based on industry-standard, open-source GNU technologies and supports standard Linux distributions as well as proprietary kernels.
“The compiler is an important feature when running large benchmarks, and it is a significant part of our strategy that we provide a GNU compiler that is open-source by definition,” added Jon Frosdick, director of software engineering at SuperH, Inc. “We are actively working with our third parties to be sure they’re able to take advantage of the features and optimizations we’ve put into this open source compiler, so that designers developing their own compilers or using this compiler in the SuperH environment will be able to take advantage of the optimizations and capabilities we’ve developed.”
CPU cores in the SH-4 family are based on a 32-bit SuperH RISC core available as a soft core or a range of hard cores optimized for different silicon processes. The published EEMBC scores are benchmarked on the SH4-202 with 2-way, 32-KB data and 16-KB instruction caches. System-on-chip products based on the SH-4 core utilize the SuperHywayTM, a configurable on-chip memory-mapped split-transaction packet-routing interconnect capable of supporting high-bandwidth and low-latency transactions.
SuperH plans to deliver “full fury” benchmarks for the SH-4 that will highlight the multimedia capabilities of the core including the 4-way vector FPU, which can process four single precision floating-point numbers in parallel.
“SuperH joined EEMBC as a board member just six months ago, so it is especially gratifying to see how quickly the company has certified and published benchmark scores on the SH-4,” said Markus Levy, EEMBC president. “Besides demonstrating the out-of-the-box performance of the SuperH core, these new scores are a significant contribution to our library of EEMBC benchmark score reports based on simulation.”
Detailed EEMBC benchmark score reports for the SuperH SH-4 are available now for free from the Search Benchmark Scores area of the EEMBC Web site or direct from the following URLs:
In addition to the SuperH SH-4, certified EEMBC benchmark scores based on simulation have been published for ARM’s ARM1020E, ARC International’s ARCtangent-A4, Improv Systems’ Jazz2020, Intrinsity’s FastMATH, and Tensilica’s Xtensa T1030 and Xtensa-V T1050.
EEMBC is a registered trademark of the Embedded Microprocessor Benchmark Consortium. VR5500 is a trademark of NEC Corporation in the United States and other countries. All other trademarks appearing herein are the property of their respective owners.