Certified Performance Analysis
for Embedded Systems Designers

EEMBC Update - March 2009

In preparation for the official certifiable release of MultiBench 1.0e, EEMBC made several enhancements to its MultiBench 1.0 benchmark software. The first enhancement is a mechanism that automatically calculates the MultiBench marks that include ParallelmarkTM, MixmarkTM, and MultimarkTM, each of which is designed to highlight a specific aspect of multicore performance, such as scalability and overall throughput.

In the second enhancement, EEMBC has included an additional option for workload data sizes. MultiBench 1.0 contained workloads with 64Mbyte data sizes, while the certification version uses datasets that limit the working set size to 4Mbytes per context. This is significant because the use of 64Mbyte data sizes can easily exceed the memory capacity of the majority of embedded multicore platforms, especially when trying to run MultiBench with multiple degrees of concurrency. The smaller 4Mbyte data sizes also make MultiBench more practical to run on software-based simulators.

The EEMBC Technology Center (ETC) performs certifications to verify the accuracy and repeatability of benchmark scores, disclosure reports, and other data submitted by companies. ETC performed the first MultiBench 1.0e certification on MIPS Technologies' MIPS32R 1004KT Coherent Processing System (CPS), a multi-threaded multiprocessor IP core.

EEMBC's MultiBench 1.0e multicore-enabled benchmarks are available for licensing now. The EEMBC Technology Center offers analysis of MultiBench results as one of its testing services. Further information is available at www.eembc.org.

EEMBC MultiBench Demo for Windows and Linux

MultiBenchTM is a suite of embedded benchmarks that allows processor and system designers to analyze, test, and improve multicore architectures and platforms. Let us know if you're interested in checking out the demo that includes several of the workloads used in this suite. Send an email to multibench-demo@eembc.org.

There will be several related presentations at the upcoming Multicore Expo being held in Santa Clara from March 16-19.

Shay Gal-On, Director of Software Engineering for EEMBC will present "Using a MultiBench Methodology to Analyze Multicore System Performance" that will show various architecture independent characteristics of the MultiBench workloads that can be used either to better understand overall performance of a platform, or to zero in on the workloads that matter most to you as they are closest to the activity expected in your system. This presentation will also show the methodology and characteristics that were obtained from traces and instrumentation on CISC and RISC architectures, and analyzed with a variety of tools.

Mark Throndson, Director of Marketing for MIPS Technologies will present "Scaling Performance on One Architecture Running Under Linux" that will discuss real-world applications where the combination of coherent multiprocessing and multi-threading can have a significant impact on
performance. It will also examine the performance and power consumption of MIPS Technologies' MIPS32 1004K coherent processing system compared to a single-threaded core, using the latest performance data on a variety of EEMBC MultiBench benchmarks.

EEMBC will also be exhibiting at Multicore Expo.

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