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	<title>EEMBC &#38; CoreMark Blog</title>
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	<link>http://www.eembc.org/wordpress</link>
	<description>This Blog focuses on EEMBC &#38; CoreMark</description>
	<lastBuildDate>Mon, 19 Jul 2010 15:17:21 +0000</lastBuildDate>
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			<item>
		<title>On inlining and other compiler optimizations</title>
		<link>http://www.eembc.org/wordpress/?p=143</link>
		<comments>http://www.eembc.org/wordpress/?p=143#comments</comments>
		<pubDate>Mon, 19 Jul 2010 15:17:04 +0000</pubDate>
		<dc:creator>shay@eembc.org</dc:creator>
				<category><![CDATA[Coremark]]></category>
		<category><![CDATA[EEMBC]]></category>

		<guid isPermaLink="false">http://www.eembc.org/wordpress/?p=143</guid>
		<description><![CDATA[CoreMark run rules allow for any compiler optimizations. Unlike Dhrystone, CoreMark relies on a design that forces any computation to happen at compile time by tracing any computation chain from a value that is not available at compile time and ends with an output.
While compilers can find more efficient ways of implementing those computations, the [...]]]></description>
			<content:encoded><![CDATA[<p>CoreMark run rules allow for any compiler optimizations. Unlike Dhrystone, CoreMark relies on a design that forces any computation to happen at compile time by tracing any computation chain from a value that is not available at compile time and ends with an output.</p>
<p>While compilers can find more efficient ways of implementing those computations, the computations cannot be done at compile time, and thus actual operation cannot be &#8220;optimized away&#8221;. Dhrystone for example was split to multiple files since the advent of the technique called <a title="inlining" href="http://en.wikipedia.org/wiki/Inline_expansion" target="_blank">inlining </a> allowed compilers to avoid performing the very tasks the benchmark was trying to analyze. Since compilers can now analyze the program even when it is split to multiple files, this cure did not work&#8230;</p>
<p>In fact, many modern architectures rely on the compiler to create code that can make efficient use of hardware resources, and restricting the compiler from optimizing is not a reasonable restriction. CoreMark does not attempt to force a specific number of branches or loads, rather only that all computations are performed at run time. Complex architectures are going to find different ways of doing those computations (e.g. SIMD, predicated execution and more), while simple architectures are going to perform the operations head on. As long as the operation is performed, the benchmark is useful to analyze the performance potential of the core.</p>
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		<item>
		<title>CoreMark Analytic Evaluation &#8211; Interview</title>
		<link>http://www.eembc.org/wordpress/?p=135</link>
		<comments>http://www.eembc.org/wordpress/?p=135#comments</comments>
		<pubDate>Tue, 08 Jun 2010 02:02:47 +0000</pubDate>
		<dc:creator>shay@eembc.org</dc:creator>
				<category><![CDATA[Coremark]]></category>
		<category><![CDATA[EEMBC]]></category>

		<guid isPermaLink="false">http://www.eembc.org/wordpress/?p=135</guid>
		<description><![CDATA[Recently Van Smith of Canalabs submitted several scores to the CoreMark website. We asked him about his choices for run parameters&#8230;
[NOTE: To put this blog into context, refer to the scores submitted on April 12 for  Intel Atom N450, VIA Nano L3050, AMD Mobile Athlon XP-M (Barton), and Freescale i.MX515 at http://coremark.org/benchmark/index.php?pg=benchmark)
Why did you use [...]]]></description>
			<content:encoded><![CDATA[<p>Recently Van Smith of Canalabs submitted several scores to the CoreMark website. We asked him about his choices for run parameters&#8230;</p>
<p><em>[NOTE: To put this blog into context, refer to the scores submitted on April 12 for  Intel Atom N450, VIA Nano L3050, AMD Mobile Athlon XP-M (Barton), and Freescale i.MX515 at http://coremark.org/benchmark/index.php?pg=benchmark)</em></p>
<p>Why did you use FORK rather then PTHREADS?</p>
<p>Answer: I used the same set of CoreMark compiler flags and settings as I had come up with several months  ago after experimenting on an AMD Phenom II system. However, these settings came directly from the best performing Intel system on CoreMark website.  Of course, forking is the most reliable way of getting multicore scaling across a broad range of platforms, which is my goal. Threading can lead to headaches in those situations.</p>
<p><span style="color: #ff9900;">*NOTE from Shay Gal-On: CoreMark actually contains 3 separate methods to use concurrency. All of them have been thoroughly validated, so feel free to pick any method you wish and tell us why you picked it&#8230;</span></p>
<p>Why did you choose to oversubscribe the cores with 4 threads?</p>
<p>Answer: I wanted to use exactly the same settings across all platforms under test. The only platform in my ARM versus x86 report to benefit from forking was the Intel Atom; if all CPUs had been single-core without HyperThreading, I would have only used one thread.  As you know, threading/forking places greater pressure on  caches and memory and I wanted to keep this consistent across all systems under test.</p>
<p><span style="color: #ff9900;">* We like this approach, though what is a fair comparison? As mentioned in previous posts, CoreMark is not really focused on multiple cores. We highly recommend using EEMBC MultiBench when trying to evaluate performance in a MultiCore environment.</span></p>
<p>Why did you under-clock the N450 to 1GHz when it normally runs at 1.66GHz? Did it change the core/bus ratio?</p>
<p>Answer: The ARM Cortex-A8 system ran at 800MHz and I wanted to have all of the platforms operate at this speed for a fair IPC performance comparison.</p>
<p>Unfortunately, the Atom N450 can only be downclocked to 1GHz, so that&#8217;s what I was forced to use.  Only the multiplier was changed on the Atom and the VIA Nano L3050; adjusting the bus clock / system clock should always be avoided in performance benchmarking for many, many obvious reasons.</p>
<p><span style="color: #ff9900;">* For processors with even a small cache, CoreMark will operate entirely inside the cache, and will not be affected by memory performance at all. This is a critical concern for small embedded devices though, as mentioned in a previous blog post.</span></p>
<p>All in all, nice to see that industry analysts are picking up CoreMark and using it to test processors at any level. Check the news section to see the latest&#8230;</p>
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		<item>
		<title>On CPU and Memory tangles</title>
		<link>http://www.eembc.org/wordpress/?p=122</link>
		<comments>http://www.eembc.org/wordpress/?p=122#comments</comments>
		<pubDate>Mon, 08 Mar 2010 23:59:20 +0000</pubDate>
		<dc:creator>shay@eembc.org</dc:creator>
				<category><![CDATA[Coremark]]></category>
		<category><![CDATA[EEMBC]]></category>

		<guid isPermaLink="false">http://www.eembc.org/wordpress/?p=122</guid>
		<description><![CDATA[Two CoreMark scores for the TI Stellaris were submitted recently. It is interesting to note that while the only difference between the submissions is the frequency, the CoreMark/MHz has changed (1.9 at 50MHz vs. 1.6 at 80MHz; a 16% drop). Since the device does not have cache, the CPU frequency to memory frequency ratio may [...]]]></description>
			<content:encoded><![CDATA[<p>Two CoreMark scores for the TI Stellaris were submitted recently. It is interesting to note that while the only difference between the submissions is the frequency, the CoreMark/MHz has changed (1.9 at 50MHz vs. 1.6 at 80MHz; a 16% drop). Since the device does not have cache, the CPU frequency to memory frequency ratio may come into effect, and indeed we find that the flash used on the device can only scale 1:1 with the CPU frequency up to 50MHz. Once frequency goes above 50MHz, the memory frequency scales 1:2 with the CPU.</p>
<p>The memory to CPU frequency ratio is a common limitation, and various technological solutions are available. Cache is one answer, but expensive in terms of silicon area and resulting cost for the end product, especially critical in low-end microcontrollers. Other solutions may have wide reads (e.g. NXP ARM7 parts read 128 bits at a time) which will speed up execution of serial blocks of code, or more advanced techniques such as the &#8220;Enhanced Flash Memory Accelerator&#8221;  (see NXP LPC1759 CPU).</p>
<p>In general, performance will not increase linearly with frequency if the code and/or data the program needs resides in memory that cannot scale at the same ratio. This will be true in benchmarks and in &#8216;real&#8217; life. Does it matter to your application?</p>
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		<title>EEMBC Director of Software Engineering takes on sumo wrestler with EEMBC power</title>
		<link>http://www.eembc.org/wordpress/?p=125</link>
		<comments>http://www.eembc.org/wordpress/?p=125#comments</comments>
		<pubDate>Sat, 06 Mar 2010 16:47:00 +0000</pubDate>
		<dc:creator>Markus Levy</dc:creator>
				<category><![CDATA[Coremark]]></category>
		<category><![CDATA[EEMBC]]></category>

		<guid isPermaLink="false">http://www.eembc.org/wordpress/?p=125</guid>
		<description><![CDATA[Shay Gal-On always wins when it comes to wrestling with EEMBC benchmarks. But he&#8217;s no match for sumo wrestler.
http://www.youtube.com/watch?v=njBGUzAExo4
]]></description>
			<content:encoded><![CDATA[<p>Shay Gal-On always wins when it comes to wrestling with EEMBC benchmarks. But he&#8217;s no match for sumo wrestler.</p>
<p><a href="http://www.youtube.com/watch?v=njBGUzAExo4" target="_blank">http://www.youtube.com/watch?v=njBGUzAExo4</a></p>
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			<wfw:commentRss>http://www.eembc.org/wordpress/?feed=rss2&amp;p=125</wfw:commentRss>
		<slash:comments>2</slash:comments>
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		<item>
		<title>What do YOU use to edit your code?</title>
		<link>http://www.eembc.org/wordpress/?p=113</link>
		<comments>http://www.eembc.org/wordpress/?p=113#comments</comments>
		<pubDate>Thu, 11 Feb 2010 15:49:17 +0000</pubDate>
		<dc:creator>shay@eembc.org</dc:creator>
				<category><![CDATA[EEMBC]]></category>

		<guid isPermaLink="false">http://www.eembc.org/wordpress/?p=113</guid>
		<description><![CDATA[Being the main software developer for EEMBC, I spend a lot of time writing code. For big projects, an IDE such as Eclipse, Visual Studio, or Multi is essential. But what about other editing needs? When you need a small Perl script? HTML page with some JavaScript? Quick edit to a small C file? Edit [...]]]></description>
			<content:encoded><![CDATA[<p>Being the main software developer for EEMBC, I spend a lot of time writing code. For big projects, an IDE such as Eclipse, Visual Studio, or Multi is essential. But what about other editing needs? When you need a small Perl script? HTML page with some JavaScript? Quick edit to a small C file? Edit a JavaScript that was encoded so that one line is more then 16K chars?</p>
<p>Every programmer needs a code editor, and once you get used to the quirks of an editor, it is hard to switch. Many still use EMACS or even VI &#8211; on some embedded platforms I use VI since it is easily available on even the most minimal Linux distribution.</p>
<p>For a graphical environment though, I like more convenience that comes with a GUI but am not willing to give up on some useful features:<br />
- Syntax highlighting<br />
- Regular expressions for find/replace<br />
- Auto code layout (smart tabs, brace matching and their ilk)<br />
- Browse/tags database support<br />
- Performance (time to initial open, time to load/edit/search large files)<br />
- Customization<br />
- Macros (Define commands and key sequences)<br />
- Bindings (the ability to customize any key combo to an editor command)</p>
<p>Other nice to have features:<br />
- Code completion<br />
- Column editing mode<br />
- Tabs for documents<br />
- Integration with external commands<br />
- Code folding<br />
- Integrated file explorer<br />
- Integrated source control (SVN)<br />
- Sessions (open up with whatever was in the editor when it was closed)<br />
- Hex edit</p>
<p>Anything else is a bonus I will gladly take but am not willing to give up<br />
convenience or speed.</p>
<p>I count 60 editors on <a href="http://en.wikipedia.org/wiki/Comparison_of_text_editors#Programming_features">http://en.wikipedia.org/wiki/Comparison_of_text_editors#Programming_features</a>, how do you choose the right one for you? I try to check what is available and try 3 new editors once a year.Sometimes I will even switch&#8230;</p>
<p>Currently on Windows I am using Notepad++. Originally I was drawn by the fact this had most of what I wanted and I had access to the source to make a few modifications. Since then this editor has matured and I no longer have a private version compiled from the source.</p>
<p>Things I wish were different but not enough to fix the source code:<br />
- Regex for find/replace could be better (e.g. just use Perl Regex)<br />
- Really long lines don&#8217;t display correctly (compressed JavaScript)</p>
<p>Other editors I have used in the past and switched from:<br />
- Slickedit (awesome editor, but cost issues when I switched to a new<br />
company)<br />
- Editplus (was not maintained for a long while. Looks like it is actively<br />
developed again, may need to check it out)<br />
- Ultraedit (somehow it just did not measure up and I ended up dropping it after a mere 3 months of use)<br />
- XEmacs (EMACS is extremely powerful, but the human interface of the GUI version doesn&#8217;t cut it)<br />
- PSpad (performance issues caused me to drop this one)</p>
<p>Which 3 editors do you think I should try in 2010?</p>
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			<wfw:commentRss>http://www.eembc.org/wordpress/?feed=rss2&amp;p=113</wfw:commentRss>
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		<item>
		<title>Data types</title>
		<link>http://www.eembc.org/wordpress/?p=94</link>
		<comments>http://www.eembc.org/wordpress/?p=94#comments</comments>
		<pubDate>Tue, 12 Jan 2010 22:27:00 +0000</pubDate>
		<dc:creator>shay@eembc.org</dc:creator>
				<category><![CDATA[Coremark]]></category>

		<guid isPermaLink="false">http://www.coremark.org/wordpress/?p=94</guid>
		<description><![CDATA[People often ask about the applicability of CoreMark for 8-, 16-, and 32-bit processors. They wonder if it provides a realistic measure of performance for an 8-bit micro when it does calculations based on 32-bit data (and vice versa). CoreMark will work on any architecture, though 8b handling is most efficient on 8b processors, 16b [...]]]></description>
			<content:encoded><![CDATA[<p>People often ask about the applicability of CoreMark for 8-, 16-, and 32-bit processors. They wonder if it provides a realistic measure of performance for an 8-bit micro when it does calculations based on 32-bit data (and vice versa). CoreMark will work on any architecture, though 8b handling is most efficient on 8b processors, 16b data types are handled optimally on 16b processors, and similarly 32b processors are the best at handling 32b data.</p>
<p>Realistically though, all of those data types are commonly used in most C code. The compiler is in charge of making the best use of the processor resources, and making sure the end result is correct.</p>
<p>CoreMark intrinsically uses  several integer data types:</p>
<p>8b &#8211; used as data for the state machine (mostly in compares).</p>
<p>16b &#8211; used as data and status info during the list processing (read/write and bit manipulation) as well as input data for the matrix operations (computations), and for crc.</p>
<p>32b &#8211; used as result data type for matrix multiply operations.</p>
<p>This introduces a mix of the common programming data types and covers core integer functionality in the processor.</p>
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		<title>Compilers Make a Difference</title>
		<link>http://www.eembc.org/wordpress/?p=67</link>
		<comments>http://www.eembc.org/wordpress/?p=67#comments</comments>
		<pubDate>Fri, 04 Sep 2009 17:05:35 +0000</pubDate>
		<dc:creator>shay@eembc.org</dc:creator>
				<category><![CDATA[Coremark]]></category>

		<guid isPermaLink="false">http://www.coremark.org/wordpress/?p=67</guid>
		<description><![CDATA[With 6 scores posted for the PIC32 starter kit, I thought we should check out the results to understand the variance.The scores submitted by using 3 different compilers: MPLAB C32 1.0 (2007) , MPLAB C 1.05 (2009), Sourcery G++4.3 (2009).
Since the microcontroller is not using cache, the memory to cpu frequency is going to make [...]]]></description>
			<content:encoded><![CDATA[<p>With 6 scores posted for the PIC32 starter kit, I thought we should check out the results to understand the variance.The scores submitted by using 3 different compilers: MPLAB C32 1.0 (2007) , MPLAB C 1.05 (2009), Sourcery G++4.3 (2009).</p>
<p>Since the microcontroller is not using cache, the memory to cpu frequency is going to make a difference.<span id="more-67"></span></p>
<p>So let us take frequency into account:</p>
<table width="447" border="0" cellpadding="2" cellspacing="2">
<tr>
<td width="73" align="center"><strong>Freq</strong></td>
<td width="213" align="center"><strong>Compiler</strong></td>
<td width="70" align="center"><strong>/Mhz</strong></td>
<td width="65" align="center"><strong> Mark</strong></td>
</tr>
<tr>
<td>30MHz</td>
<td>GCC 4.3.2  -O3</td>
<td align="right">2.599</td>
<td align="right">77.973</td>
</tr>
<tr>
<td>30MHz</td>
<td>MPLAB C v1.05 -O3</td>
<td align="right">2.426</td>
<td align="right">72.78</td>
</tr>
<tr>
<td>72MHz</td>
<td>MPLAB C32 v1.00  -O2        </td>
<td align="right">1.712</td>
<td align="right">123.264</td>
</tr>
<tr>
<td>72MHz </td>
<td>MPLAB C32 v1.00  -O3</td>
<td align="right">1.899</td>
<td align="right">136.728</td>
</tr>
<tr>
<td>80MHz</td>
<td>GCC 4.3.2  -O3</td>
<td align="right">2.297</td>
<td align="right">183.762</td>
</tr>
<tr>
<td>80MHz</td>
<td>MPLAB C v1.05 -O3</td>
<td align="right">2.040</td>
<td align="right">163.234 </td>
</tr>
</table>
<p>We can see that the compilers from 2009 are both pretty close. There is no data in the submission on the number of wait states used for the flash with the MPLAB compiler, but Konstantin Yurkevich of Rovalant Inc sent us the project and port he used when submitting the scores (which you can find in the CoreMark download section).</p>
<p>We can also see that even with the same compiler, there is a difference of ~10% between different optimization levels (-O2 to -O3).</p>
<p>The compiler from 2007 creates code that is ~20% slower then the best submitted score, showing that the compiler has matured in 2 years (I would hope it would). More importantly, it shows that the compiler and compiler flags used must be included along with the score, as without that information the score is not reliable or repeatable!<!--more--></p>
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		<title>Running Coremark</title>
		<link>http://www.eembc.org/wordpress/?p=62</link>
		<comments>http://www.eembc.org/wordpress/?p=62#comments</comments>
		<pubDate>Thu, 30 Jul 2009 16:34:06 +0000</pubDate>
		<dc:creator>shay@eembc.org</dc:creator>
				<category><![CDATA[Coremark]]></category>

		<guid isPermaLink="false">http://www.coremark.org/wordpress/?p=62</guid>
		<description><![CDATA[For those who don&#8217;t like reading the readme&#8230;
Running on a Linux platform with a native toolchain:
Open up linux/core_portme.h (or linux64/core_portme.h on a 64b platform), and check all predefined macros (for example endianness) for your platform.
Make Results are in run1.log and run2.log.
For a cross hosted toolchain, edit the file linux/core_portme.mak. You need to define how to [...]]]></description>
			<content:encoded><![CDATA[<p><span>For those who don&#8217;t like reading the <span>readme</span>&#8230;</span></p>
<p><span>Running on a Linux platform with a native <span>toolchain</span>:</span></p>
<p><span>Open up linux/core_portme.h (or linux64/core</span><span>_portme.h on a 64b platform), and check all predefined macros (for example endianness) for your platform.</span></p>
<p>Make Results are in run1.log and run2.log.<span id="more-62"></span></p>
<p><span>For a cross hosted <span>toolchain</span>, edit the file linux/core_portme.<span>mak</span>. You need to define how to load the binary to the target and how to run it. If the target supports ssh, just <span>un-comment</span> the LOAD and RUN sample using ssh.</span></p>
<p>What if there is no OS running on the board?</p>
<p>1. Create a new folder.</p>
<p><span>2. Copy the <span>barebones</span> content to the new folder.</span></p>
<p><span>3. Edit the 3 files in the new folder, adding functionality for timing and output, and setting <span>toolchain</span> options.</span></p>
<p><span>* You may want to use basic sample code for UART (or debugger output) and timer for your board. Sample code is usually available with your embedded <span>toolchain</span> or kit.</span></p>
<p>&gt; make</p>
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		<title>Using Coremark on Multiple Cores</title>
		<link>http://www.eembc.org/wordpress/?p=48</link>
		<comments>http://www.eembc.org/wordpress/?p=48#comments</comments>
		<pubDate>Mon, 08 Jun 2009 16:00:59 +0000</pubDate>
		<dc:creator>shay@eembc.org</dc:creator>
				<category><![CDATA[EEMBC]]></category>

		<guid isPermaLink="false">http://www.coremark.org/wordpress/?p=48</guid>
		<description><![CDATA[Although we don&#8217;t recommend using this because it will only yield a linear performance increase, CoreMark standard allows for execution of multiple copies on multiple cores, and in fact already contains 3 common implementations (PThreads, Fork(with shared memory) and Sockets). The portable layer allows extension to other proprietary mechanisms as well. E5405 scores posted recently [...]]]></description>
			<content:encoded><![CDATA[<p style="text-align: left;">Although we don&#8217;t recommend using this because it will only yield a linear performance increase, CoreMark standard allows for execution of multiple copies on multiple cores, and in fact already contains 3 common implementations (PThreads, Fork(with shared memory) and Sockets). The portable layer allows extension to other proprietary mechanisms as well. E5405 scores posted recently for 1,2 and 4 cores show a linear speedup with the number of cores used. How come?<span id="more-48"></span></p>
<p style="text-align: left;">CoreMark aims at measuring <strong>core </strong>efficiency, and nothing else. Multiple copies of coremark would (assuming decent scheduling by the underlying scheduler or OS) each operate on a single core. There is no interaction between multiple copies of CoreMark, and synchronization only occurs at the end of the run. Thus we would expect execution of multiple copies to simply result in linear speedup &#8211; and indeed the posted scores show linear speedup (or as close as makes no difference). When comparing CoreMark scores, make sure to check the compiler flags and parallel options.</p>
<p style="text-align: left;">For true analysis of multi-core devices, system factors such as cache coherency and bus arbitrations mechanisms also need to be considered, as does the efficiency of synchronization primitives and the underlying scheduler (or OS). Head to the <a title="EEMBC" href="http://www.eembc.org" target="_self">EEMBC</a> website and check out <a title="MultiBench" href="http://www.eembc.org/benchmark/multi_sl.php" target="_blank">MultiBench </a>for more comprehensive analysis of multi-core systems.</p>
<div id="attachment_47" class="wp-caption aligncenter" style="width: 501px"><a rel="attachment wp-att-47" href="http://www.eembc.org/wordpress/?attachment_id=47"><img class="size-full wp-image-47" title="coremark_cores" src="http://www.coremark.org/wordpress/wp-content/uploads/2009/06/coremark_cores.jpg" alt="E5405 Speedup" width="491" height="261" /></a><p class="wp-caption-text">E5405 Speedup</p></div>
<p style="text-align: left;">
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		<title>Concurrency Analysis on CoreMark</title>
		<link>http://www.eembc.org/wordpress/?p=32</link>
		<comments>http://www.eembc.org/wordpress/?p=32#comments</comments>
		<pubDate>Sat, 06 Jun 2009 19:52:27 +0000</pubDate>
		<dc:creator>Markus Levy</dc:creator>
				<category><![CDATA[Coremark]]></category>
		<category><![CDATA[EEMBC]]></category>

		<guid isPermaLink="false">http://www.coremark.org/wordpress/?p=32</guid>
		<description><![CDATA[Although the current run rules for CoreMark don&#8217;t allow messing with the code, it&#8217;s an interesting exercise to see how much concurrency can be extracted from this relatively sequential benchmark code. CriticalBlue took this on with its Prism tool, writing up an interesting article on the process and results. Check it out
]]></description>
			<content:encoded><![CDATA[<p>Although the current run rules for CoreMark don&#8217;t allow messing with the code, it&#8217;s an interesting exercise to see how much concurrency can be extracted from this relatively sequential benchmark code. CriticalBlue took this on with its Prism tool, writing up an interesting article on the process and results. <a target="_blank" href="http://www.criticalblue.com/criticalblue_products/pdf/CriticalBluePrismCoremarkPt1.pdf">Check it out</a></p>
]]></content:encoded>
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