Industry-Standard Benchmarks for Embedded Systems
EEMBC, an industry alliance, develops benchmarks to help system designers select the optimal processors and understand the performance and energy characteristics of their systems. EEMBC has benchmark suites targeting cloud and big data, mobile devices (for phones and tablets), networking, ultra-low power microcontrollers, the Internet of Things (IoT), digital media, automotive, and other application areas. EEMBC also has benchmarks for general-purpose performance analysis including CoreMark, MultiBench (multicore), and FPMark (floating-point).

Academic Licensee Research

The EEMBC Academic licensees listed below have graciously agreed to share their research interests relative to EEMBC benchmarks.

Abo Akademi University
Dept of Information Technology
Johan Lilius

The Embedded Systems Laboratory performs research on multi-core architectures, and programming languages for highly parallel and distributed architectures. The application areas that we target include future multi-media applications, low-power architectures, and software defined radio. Our approach is based on a model-driven design methodology, where the systems behavior can be specified at different levels of abstraction, and emphasizing particular aspects that are relevant at that level. The design flow leads to implementations in the language Canals, which is a dataflow or streaming language, that allows explicit specification of communication patterns, dataflows and in particular scheduling strategies at different levels of granularity. The Canals application is then mapped onto a heterogenous multi-core architecture.

Academic Sinica
Jan-Jan Wu

Developing dynamic binary translator for cross-isa emulation, and using the EEMBC benchmarks to evaluate the performance of the translator. We optimize the translation algorithm and compiler technique to improve the performance of QEMU based on the evaluation result of EEMBC.

Barcelona Supercomputing Center
Francisco J. Cazorla Almeida

EEMBC will be used in the PROARTIS project ( PROARTIS hypothesis is that new advanced hardware/software features (such as caches or multicore processors) enabling truly randomized timing behaviour can be defined for use in critical real-time embedded (CRTE) systems. This paradigm shift will permit probabilistic analysis techniques to be used effectively in arguments of system verification and certification, by demonstrating that the probability of pathological execution times is negligible.

Bogazici University
Department of Computer Engineering
Assoc. Prof. Alper Sen

Prof. Sen plans to develop synthetic embedded multicore benchmarks from EEMBC benchmarks. Specifically, he will utilize EEMBC MultiBench that will allow them to develop synthetics for multicore architectures. Their synthetics will be much smaller than the original benchmarks but similar to them with respect to some performance characteristics. In order to obtain portability, they will use the newly developed standards from Multicore Association for communication and resource sharing (namely MCAPI and MRAPI libraries).

Brown University
Iris Bahar

In our project, we are interested in evaluating the energy-efficiency and performance of a number of synchronization mechanisms adapted for embedded devices. We are focusing on providing simple hardware accelerators (and in particular transactional memory) for common software synchronization patterns found in embedded systems. We are evaluating our designs on a simulation framework we developed. To properly evaluate our designs, we are looking to run benchmarks representative of multicore applications for embedded systems. We believe the EEMBC benchmarks will provide us with useful insights into designing our embedded system.

Carnegie Mellon University
Electrical and Computer Engineering
James C Hoe

Current research focuses on computer architecture, processor microarchitecture, simulation and FPGA emulation of computer systems, and tools for high-level hardware design and synthesis

Chalmers University of Technology
Dept. of Computer Science and Engineering
Per Stenstrom

The research we are doing based on EEMBC focuses on two topics. 1. We are doing research in a new class of reconfigurable architectures for the embedded space that promises to exhibit high energy-efficiency and performance while at the same time being able to adapt to workloads. We want to use EEMBC to evaluate this new architectural style which we have called FlexSoC. 2. We are also doing research in novel programming interfaces for multicore architectures. To this end, we are specifically interested in how well emerging transactional memory models can help applications in the embedded space to leverage on the compute power of multicores. We are using EEMBC to quantitatively provide empirical data for this.

Dongguk University Korea
Kangwoo Lee

My fundamental research interest lies in Computer Architecure. Previously, for the last decades or so, I was studying the memory architecture including caches in multiprocessor systems. The application domain for such systems are scientific computations and commercial applications. For the scientific applications, Stanford's SPLASH benchmark suites and, for the commercial applications, TPC benchmarks were used. Recently, I have become interested in embedded system architectures and printer systems in particular. Having licensed the EEMBC Office Automation benchmarks, I will be doing performance evaluations for a certain commercial printer system. The goal of the research is to find a methodology for designing best-performing and well-tuned printer systems. In addition, I have formed a team with my colleagues to study embedded systems for mobile systems. Networking and communication issues will be included.

Ecole Polytechnique Federale de Lausanne
Paolo Ienne

Processor Architecture Laboratory (LAP) At LAP (Processor Architecture Laboratory) we perform research in the area of innovative embedded-system architectures, including automated instruction set extensions, low-power memory hierarchies, and multiprocessor-on-chip.

Electronics and Telecommunications Research Institute (ETRI)
Youngsu Kwon

ETRI is designing and testing its Aldebaran Core, a 32-bit RISC core for many-core CPU. The dual-issue superscalar Aldebaran comprises 32KB/32KB I and D caches, 32/32-entry MMU, and four execution units in parallel running Linux optimized for many-Core CPU. The next-generation 64-core Aldebaran has the SMT architecture where each core cluster includes shared I and D caches as well as four instruction-computing units.

Gang Shi

The Loongson group of ICT CAS China is involved in the research and development of general purpose processors. We are using the EEMBC benchmarks to evaluate the performance of the processors. We optimize the architecture and implementation technique to improve the performance of Loongson processor based on the evaluation result of EEMBC.

Florent de Dinechin

FPMark license

Kyoto University
Taiichi Yuasa

We are developing real-time garbage collection algorithms for embedded systems. We have developed return barrier GC replication-based incremental compaction algorithms. We implemented them on a Java VM for mobile phones and evaluated it using EEMBC GrinderBench benchmarks. Now we modifying the algorithm to improve its performance. Publications: H. Saiki, Y. Konaka, T. Komiya, M. Yasugi, and T. Yuasa. "Real-time GC in JeRTy VM using the return-barrier method". In Proceedings of ISORC 2005, pages 140-148. T. Ugawa, M. Yasugi, and T. Yuasa. "Replication-Based Incremental Compaction". In Proceedings of ISORC 2008, pages 516-526.

La Trobe University
Center for Technology Infusion
Jugdutt (Jack) Singh
Aniruddha Desai

We are developing a configurable architecture for a hardware-based Java processor for real-time and portable applications. We use EEMBC benchmarks for workload characterization and performance evaluation of our design.

Mälardalen University
Computer Science & Engineering
Dr. Andreas Ermedahl

Our main research focus is on Worst-Case Execution Time (WCET) analysis. Such analyses are used to derive an upper bound on the possible running time of computer programs. Derived timing bounds are key components for validating embedded real-time systems and to guarantee that no deadlines will be missed. The EEMBC benchmarks will be used to test and evaluate our developed WCET analysis techniques. Our project homepage can be found at:

Manchester Metropolitan University
Computing Science
Andy Nisbet

I will be working on value reuse and value locality optimizations for embedded processor architectures.

Michigan Tech University
Computer Science & Engineering
Zhenlin Wang

The Department of Computer Science at Michigan Tech collaborates with LSI to evaluate the effectiveness of GCC targeted to the new PowerPC 476 processor. Our goal is to assess the quality of code generated by the GCC PowerPC 476 target and to look for potential missed opportunities to apply 476-specic optimizations. We will use EEMBC Networking 2.0 and other related benchmarks for this evaluation.

Nanyang Technological University
Thambipillai Srikanthan

Centre for High Performance Embedded Systems (CHiPES) CHiPES is involved in the research and development of high performance embedded systems. Current research areas include design methodologies for constraint-aware techniques, reconfigurable computing, embedded software, and architectural translations of complex algorithms.

National Taiwan University
Chi-Sheng Shih

We are using EEMBC benchmarks to evaluate our design of an embedded real-time operating systems on multi-core SoC systems. The systems is still in progress and should have our preliminary results in mid-2008.

National Taiwan University 2
Computer Engineering
Chia-Lin Yang

Multi-core architecture: Programming tool, Design and Analysis, Thread Allocation, Thread Scheduling, Memory hierarchical design, memory structure, memory contoller design, Low power design, 3D-IC desgin, Network-on-chip design GPU architecture design, next-Generation Non-Volatile Memory Storage System MPSoC: Tool, Analysis and Design, Design Space Exploration, Electronic System Level design

National Tsing Hua University
Computer Science
Jenq-Kuen Lee

The research we are doing based on EEMBC is mainly on the compiler technologies for VLIW DSP processors, especially for the family of DSP processors with distributed register files and multi-bank register files. To reduce the design complexity and power consumptions of VLIW DSP processors, distributed register files and multi-bank register architectures are used to reduce the amount of read/write ports needed. In addition, the register files shared by multiple functional units might not be accessible to a particular functional unit at all times to further reduce the amount of read and write ports by taking advantage of DSP application characteristics. The appearance of VLIWDSP processors with highly fragmented register file designs presents a great challenge for compilers to generate efficient codes for multimedia applications. Advanced compiler optimization techniques currently being developed in our group for such architectures include SIMD optimization schemes, low-power compiler optimization schemes, SWP schemes for distributed register files, and programming models for multi-core DSP environments. We are using the EEMBC benchmarks to evaluate the performance of our optimizing compiler schemes.

Northeastern University
David Kaeli

We are using EEMBC to investigate how to balance performance and power of the Blackfin BF53x embedded environment by exploiting the availability of the performance counters on the Blackfin. We are running the EEMBC benchmarks while applying profile-guided dynamic voltage and frequency scaling on the embedded system and trying to reduce the DSP's energy consumption without significant performance degradation.

PUSAN National University
Bumjoo Shin

Currently, my research interest is to improve performance of a non-commercial JVM.

RWTH Aachen University
Software for Systems on Silicon (SSS)
Rainer Leupers

We use EEMBC as benchmark in our research on application specific instruction set processor (ASIP) design tools and automated instruction set customization.

Saarland University
Computer Engineering
Reinhard Wilhelm

Our group is researching timing analysis in embedded systems. The computation of sound and precise bounds on worst-case execution times for embedded software is imperative for hard real-time systems. Standardized benchmarks enable us to compare our approaches with those of other research teams in the are of timing analysis. Furthermore, we can identify threats to the predictability of systems in the restricted setting of well-defined programs.

Stanford University
Department of Electrical Engineering
Professor Kunle Olukotun

Currrent research projects in the Pervasive Parallelism Laboratory focus on domain specific languages (DSLs) and specialized architectures.

Technion - Israel University of Technology
Electrical Engineering
Israel Cidon

We are performing research on scheduling applications for chip multiprocessors (CMP) focusing on embedded systems workloads. The research explores the tradeoffs between performance and power taking in consideration the special characteristics of embedded workloads and applications. We are using EEMBC benchmark to evaluate our theoretical models in the embedded environment.

Technische Universität Braunschweig
Philip Axer/Prof Dr Ing Rolf Ernst

The development process of automotive embedded systems is highly complex and challenging. We meet the challenge of estimating the system time behavior of whole systems in early design phases. In this context we are investigating and developing different methods to predict the SW execution time. These methods are based on an adaption of a generic processor model to a real processor. Such a training process requires benchmarks that have to cover a wide range of SW characteristics of different domains. Therefore, we are using EEMBC benchmarks as they fulfill this requirement excellently.

Prof. Mladen Berekovic
Thomas Schuster
Increasing the computational power of today??™s processor architectures is a challenging task. Since further raising the clock rates by purely optimizing the underlying CMOS technology becomes more and more complicated, the future lies in massive parallel architectures. We are contributing to the research in this field by the development of a flexible multi-processor platform (many-core). Our focuses are the hardware-software interface and the exploration of scalability limits. To acquire realistic performance feedback, we need a set of real-life application benchmarks. EEMBC suits our requirements perfectly.

Laboratoire d'Analyse et d'Architecture des Syst
Jacques Collet

We are studying the execution variability of automotive applications. By execution variability, we mean the dispersion of the execution times, which depends on many factors, for instance:

UC Berkeley
David Patterson

We are examining whether seven or so kernels can capture the essence of future parallel computation in many different arenas. We use EEMBC to see how well these kernels cover the embedded computing arena.

University of Aizu
Hitoshi Oi

The areas of my interest are computer architecture, workload analysis, and performance evaluation. I have been using GrinderBench from EEMBC to evaluate techniques to improve the performance of Java Virtual Machine for embedded platforms.

University of Augsburg
Institute of Computer Science
Theo Ungerer

Our research in the embedded systems research group of University of Augsburg focuses on hard real-time capable design of embedded processors and system software. The EEMBC benchmarks are used for comparison of simulated research prototypes within the CAR-SoC project (see: and will also be distributed to the partners within the HiPEAC Network of Excellence cluster on Multithreaded Real-time of the European Community that perform research based on the CAR-SoC processor prototype.

University of B.C
Department of Electrical and Computer Engineering
Guy Lemieux

Project title: Soft Processors for FPGAs Project leaders: Prof. Guy Lemieux and Prof. Tor Aamodt Researchers: Aaron Severance and Saurabh Sant We are designing new soft processors and soft processor accelerators for FPGAs. The EEMBC suite provides us with a standardized method for measuring, reporting, and comparing performance to track our progress.

University of Cambridge
Computer Laboratory
Robert Mullins

Our research project is currently exploring a range of massively-parallel single-chip architectures that place the on-chip network at the heart of their design. Our simple cores are far more deeply interconnected to each other than traditional designs and support a wide-range of parallel execution patterns. This approach permits an overlay, or virtual architecture, to be constructed that matches the most natural/efficient implementation strategy for a given application in order to reduce development time, boost performance and reduce power consumption.

University of Edinburgh
School of Informatics
Nigel Topham
Bjoern Franke

We use the EEMBC benchmarks in a number of research projects on embedded processor design and implementation, compiler optimisation and automatic parallelisation. The particular research areas in which we have used the benchmarks include instruction set customisation for application-specific processors, machine-learning of compiler optimisations and phase ordering, code generation for complex instruction patterns, fast and cycle-approximate simulation methodology, and automatic extraction and exploitation of coarse-grain application parallelism.

University of Hertfordshire
School of Computer Science
Colin Egan

We use the EEMBC in one of the most important areas of contemporary research in computer engineering: energy efficiency. We focus our work onto reducing the energy efficiency of costly branch predictors by dynamically hand-shaking profiled static predictions/branch removal together with a low energy branch predictor. We demonstrate that the majority predictor accesses and predictor updates are not necessary, thereby achieving saving significant amounts of energy. Our work also shows that the use of costly predictors in terms of both energy and silicon space is also not necessary.

University of Lugano (USI)
Faculty of Informatics
Laura Pozzi

We investigate the area of novel reconfigurable fabrics, especially coarse grain, and also that of special purpose processors. As particular care is placed not only in the way to design architectures, but also in how to compile current applications onto them, experimentation with current benchmarks is a must.

University of Michigan
Electrical Engineering & Computer Science
Trevor Mudge

We are involved in some research with ARM in which we are using EEMBC benchmarks.

University of North Texas
Krishna Kavi

We have used subsets of the EEMBC benchmarks, as well as similar benchmarks, to evaluate optimal cache configurations. See the following publications: A. Naz, K. Kavi, W. Li and Philip Sweany. "Tiny split data caches make big performance impact for embedded applications," the Journal of Embedded Computing (Special Issue on Embedded Single-Chip Multi-core Architectures from System Design to Application Support), Vol.2, No.2, pp 207-219, November, 2006. Afrin Naz, Krishna Kavi, JungHwan Oh and Pierofranco Foglia. "Reconfigurable split data caches: A novel scheme for embedded systems," Proceedings of the 22nd Annual ACM Symposium on Applied Computing, Seoul, Korea, March 11-15, 2007, pp 707-7112. Afrin Naz, Krishna Kavi, Philip Sweany and Wentong Li. "A study of reconfigurable split data caches and instruction caches," Proceedings of the 19th ISCA Parallel and Distributed Computing Systems, Sept 20-22, 2006, San Francisco, CA.

University of Queensland
Electrical Engineering
Neil Bermann

The University of Queensland is undertaking research to identify the performance benefits of using specialised DSP processor architectures for the design of softcore processors on FPGAs. This research investigates the performance benefits on FPGAs of techniques including single-cycle MACs, data address generators for zero-overhead loops, and multi-port memory architectures.

University of Rochester
Martin Margala

My primary research interests are in reconfigurable parallel low energy high throughput architectures and design for reliability of multi-gigahertz circuits and systems.

University of Texas at Austin
Department of Computer Sciences
Doug Burger

We are working on designing novel, power-efficient microprocessor architectures for high-performance embedded computing. With my colleagues. We have developed the TRIPS architecture, which defines a new instruction set and efficient, sixteen-wide-issue micro-architecture.

University of Toronto
Jonathan Rose
J. Gregory Steffan
Peter Yiannacouras

We are using the EEMBC benchmarks to evaluate the performance of processor-based systems which are implemented on FPGAs. We attempt to leverage the programmability in the device to tailor the processor to the designer's speed, area, and power/energy requirements. The EEMBC benchmarks provide us with credible performance measurements which match the rigor with which we attain area, clock frequency, and power/energy measurements.

University of Waterloo
Electrical & Computer Engineer
Sebastian Fischmeister

My primary research interests include timing-aware and real-time capable software abstractions and tools for operating systems and middleware in distributed real-time embedded applications. Current applications domains include medical devices, automotive systems, and avionics. We're going to use EEMBC for our work on instrumentation, runtime monitoring, and real-time operating systems.

Department of Computer Science
An Hong

We are from Embedded System Lab of USTC. We are working on the project to build a hetergenous multiprocessor platform with Microblaze and accelerators, with Xilinx tools. We need to run the benchmarks on the development board and do some profiling to see whether our infrastructure